University of Nottingham Malaysia
Faculty of Engineering

Image of T. Nandha Kumar

T. Nandha Kumar

Associate Professor,



Dr.T. Nandha Kumar received his Bachelor and Master degrees from University of Madras and National Institute of Technology, India respectively. Subsequently he obtained Ph.D. in Electrical and Electronic Engineering from The University of Nottingham. Currently he is working as an associate professor at The University of Nottingham, Malaysia. Prior to this, he was working at Intel Corporation as a senior pre-silicon validation engineer and involved in the gate level validation of IO chips ICH4 and ICH5. He also worked as the gate level validation lead for ICH6 IO chip and RTL validation lead for legacy units of ICH7 and ICH8 IO chips.

Dr. Nandha has 21 years of academic and 4 years of Industrial experience. His research interests are in the field of Emerging Non-volatile memory, VLSI design, Test, fault/defect tolerance of digital systems, and Approximate Computing. He has published more than 90 papers in the reputed International journals and conferences. His team's work on NV memory has been selected by Institute of Physics (IOP) "Semiconductor Science and Technology" as one of the HIGHLIGHTS of 2015. Also his team's work on approximate computing has been nominated for BEST PAPER AWARD in DATE 2016 and his team's article on approximate computing has been ranked TOP 11 for the year 2018 in IEEE Transactions on Computer. An article on NVLUT by his team has been awarded BEST PAPER in Regional Symposium on Micro and Nanoelectronics 2019. He is currently supervising 4 PhD students and successfully supervised 3 PhD students to completion. He has secured research grant of about RM 1.6 million. He has contributed to three books published by IET, CRC and Springer.

He serves as an Associate Editor of IET Circuits, Devices and Systems, reviewer for IEEE Transaction on Nanotechnology, IEEE Transactions on Emerging Topics in Computational Intelligence, IEEE Transactions on Circuits and Systems 1 Regular, IET Journal of Engineering, Elsevier Microprocessor and Microsystems, Elsevier Microelectronics, Elsevier Measurement. Also he served as a technical committee member for more than 100 IEEE international conferences. He is the Tutorial chair for the Asian Test Symposium 2020.

Dr.Nandha is a Fellow of Higher Education Academy (UK), Charted Engineer (UK), Senior member IEEE, Member IET and Member TRIZ association.

Teaching Summary

1. VLSI Design (H63VLSI) - Spring

2. HDL for Programmable Logic (H64HPL) - Autumn

3. HDL for Programmable Logic with project (H64HPP) - Year Long

Research Summary

Research interests and projects:

  1. Emerging Non-Volatile Memory
  2. Nano Electronics
  3. Approximate Computing
  4. Reliability testing of reconfigurable integrated circuits such as field programmable gate arrays (FPGA).
  5. VLSI Design
  6. Hardware realization - FPGA Based

Selected Publications

1. VLSI Design

2. HDL for Programmable Logic with/without Project

3. Digital Electronics

Faculty of Engineering

University of Nottingham Malaysia
Jalan Broga, 43500 Semenyih
Selangor Darul Ehsan

telephone: +6 (03) 8924 8000
fax: +6 (03) 8924 8001

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