University of Nottingham Malaysia
     
  
 

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Kumar T. Nandha

Professor of Electronics,

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Biography

  • Professor T.Nandha Kumar, PhD, CEng(UK), Senior Member IEEE, Fellow HEA(UK), MIET

  • Prof. Nandha obtained his Bachelor's and Master's degrees from the University of Madras and the National Institute of Technology, India, respectively, and earned his PhD in Electrical and Electronic Engineering from the University of Nottingham. He joined the University of Nottingham Malaysia in 2005 as an Assistant Professor and is currently a Professor of Electronics. He has also served as the Head of the Department of Electrical and Electronics Engineering at the University of Nottingham Malaysia, contributing to academic leadership and strategic development.

    Prior to his academic career, Prof. Nandha worked at Intel Corporation as a Senior Pre-Silicon Validation Engineer, where he was involved in the gate-level validation of the ICH4 and ICH5 IO chips. He later served as the Gate-Level Validation Lead for the ICH6 IO chip and as the RTL Validation Lead for the legacy units of the ICH7 and ICH8 IO chips.

    He has over 21 years of academic experience and four years of industry experience. His research interests include emerging non-volatile memory (memristors), VLSI design and testing, fault and defect tolerance of digital systems, FPGA-based systems, in-memory computing, neuromorphic computing, and approximate computing. He is a recipient of the Lord Dearing Award for outstanding contributions to teaching and student learning at the University of Nottingham.

    Prof. Nandha has published over 100 papers in leading international journals and conferences. He currently supervises three PhD students and has successfully supervised ten PhD students to completion. He has secured approximately RM 2 million in research grants and has contributed to six books published by IET, CRC Press, and Springer.

    He previously served as an Associate Editor of the IEEE Open Journal of the Computer Society until 2025 and currently serves as an Associate Editor of IET Circuits, Devices & Systems. He is a regular reviewer for several leading IEEE, IET, and Elsevier journals. He has served on the technical committees of more than 100 IEEE international conferences and was the Tutorial Chair for the Asian Test Symposium 2020. He is also an Adjunct Professor at VIT University, India.

    His research has received multiple international recognitions, including a Highlight of 2015 by the Institute of Physics journal Semiconductor Science and Technology, a Best Paper Award nomination at DATE 2016, a Top 11 ranking in 2018 in IEEE Transactions on Computers, and Best Paper Awards at IEEE conferences between 2019 and 2021.

    Prof. Nandha is a Fellow of the Higher Education Academy (UK), a Chartered Engineer (UK), a Senior Member of IEEE, and a member of IET and the TRIZ Association.

Expertise Summary

Teaching Summary

1. VLSI Design (EEEE3032) - Spring

2. HDL for Programmable Logic (EEEE4076) - Autumn

3. HDL for Programmable Logic with project (EEEE4075) - Year Long

4. Digital Electronics ( EEEE1029 & EEEE1032) - Autumn

Research Summary

Research interests and projects:

  1. Emerging Non-Volatile Memory
  2. Approximate Computing
  3. Neuromorphic Computing
  4. In memory Computing
  5. Reliability testing of reconfigurable integrated circuits such as field programmable gate arrays (FPGA).
  6. VLSI Design
  7. Hardware realization - FPGA Based

Selected Publications

1. VLSI Design (EEEE3032) - Spring

2. HDL for Programmable Logic (EEEE4076) - Autumn

3. HDL for Programmable Logic with project (EEEE4075) - Year Long

4. Digital Electronics ( EEEE1029 & EEEE1032) - Autumn

University of Nottingham Malaysia

Jalan Broga, 43500 Semenyih
Selangor Darul Ehsan
Malaysia

telephone: +603 8924 8000
fax: +603 8924 8001
email: enquiries@nottingham.edu.my